Visit Andes’ Exhibition Hall Display to View Live Demonstrations of its Leading-Edge CPU IP Technology
Hsinchu, Taiwan , Nov. 30, 2021 (GLOBE NEWSWIRE) — Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International will contribute five presentations at the RISC-V Summit from December 6 to 8, 2021. The company will also demonstrate its latest RISC-V IP in a prominent booth in the RISC-V Summit Exhibition Hall.
Andes President and CTO, Dr. Charlie Su, will deliver the keynote speech “Beefing Up the Datacenter Accelerators” on December 7 at 1:45 PM. On December 8 at 4:00 PM, Dr. Paul Ku, Deputy Technical Director of Architecture Div., will provide IOPMP updates in his presentation “The Protection of IOPMP.”
According to the ResearchAndMarkets report released in September this year, the global market for data center accelerators should grow from $13.5 billion in 2021 to $66.4 billion by 2026, at a compound annual growth rate (CAGR) of 37.6 percent for the period of 2021-2026. Design teams are being challenged to come out a scalable architecture with a limited power budget in a short time window. To address this, Dr. Su will identify the best-in-class, off-the-shelf processor IP for the task. His Keynote will explain how Andes’ RISC-V solutions help designers customize their designs to meet the high-performance goals, tightly couple them with hardwired engines, and integrate the customized processor compilers with their AI model compilers.
Additionally, Toolchain Group Manager, Dr. I-Wei Wu, will introduce “Performance of TVM AutoScheduler for Andes Vector Processor.” Chun-Wei Shu, Software Engineer, will discuss “Bring Multicore RISC-V and Zephyr RTOS Together.” In addition, Academia Sinica in collaboration with National Tsing Hua University, Taiwan and Andes will present “Sail Specification for RISC-V P-Extension.”
For more information, please visit the RISC-V Summit website.
- Dr. Charlie Su’s presentation “Beefing Up the Datacenter Accelerators” will start on December 7 at 1:45 PM.
- Academia Sinica, National Tsing Hua University, Taiwan and Andes, will present “Sail Specification for RISC-V P-Extension” on December 7 at 3:30 PM.
- Dr. I-Wei Wu will introduce “Performance of TVM AutoScheduler for Andes Vector Processor” on December 8 at 11:00 AM.
- Chun-Wei Shu’s presentation “Bring Multicore RISC-V and Zephyr RTOS Together” will occur on December 8 at 11:15 AM.
- Dr. Paul Ku will present IOPMP updates on “The Protection of IOPMP” on December 8 at 4:00 PM.
About Andes Technology Corp.
Sixteen years in business and a Founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020 and continues to rise. To the end of Q3 2021, the cumulative volume of Andes-Embedded™ SoCs has reached 9 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube!
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